1. Field of the Invention
The present invention relates to an inspection technology of an information write state upon writing information on the structure of a logical circuit with an optical signal on an optically reconfigurable gate array.
2. Description of the Related Art
Recently, as a logical device that can reconfigure a circuit logical structure in accordance with purposes by electrically inputting a logical structure, a field programmable gate array (Field Programmable Gate Array: hereinafter, referred to as an “FPGA”) is widely used. However, the FPGA uses the structure for connecting a memory that stores information on the circuit structure and a reconfigurable gate array VLSI with a metallic wiring, and the FPGA therefore has a limitation for reducing a reconfiguring time of the circuit logical structure.
Then, recently, as a technology for dramatically reducing the reconfiguring time of the circuit logical structure, an optically reconfigurable gate array (Optically Reconfigurable Gate Array: ORGA) is searched and developed (refer to, e.g., Patent Documents 1 to 4 and Non-Patent Documents 1 to 4). The optically reconfigurable gate array is a device comprising two parts of an optical unit that outputs information on the circuit logical structure as an optical signal pattern and a VLSI unit that configures the circuit logical structure in accordance with the optical signal pattern, and executes the reconfiguration of the logical structure of the VLSI unit with the optical signal pattern from the optical unit in parallel. In general, as an optical memory that stores information on the structure of the logical circuit in the optical unit, a commutative medium is used to freely change the information on the circuit structure.
In the optically reconfigurable gate arrays, optically reconfigurable bit elements are provided at circuit positions in a chip (logical circuit chip) having a logical-circuit serving as the VLSI unit, and an optical signal pattern including the information on the configuration of the logical circuit is electrically converted into an electrical signal. The input information on the structure of the logical circuit is stored in the circuit. Further, the circuit connection is switched in accordance with the information on the configuration of the logical circuit, thereby reconfiguring the logical circuit.
As mentioned above, in the optically reconfigurable gate array, the optical unit and the VLSI unit (logical circuit chip) are arranged as independent parts. Therefore, various factors including the positional displacement of light emission and out-of-focusing cause a write error upon writing the information on the configuration of the logical circuit to the VLSI unit. The write error causes abnormal operation of the VLSI unit. Thus, it is inevitable for the optically reconfigurable gate array to inspect in advance the information write state of the VLSI unit.
Then, a dedicated circuit for inspecting the write state of the optically reconfigurable bit element (hereinafter, referred to as a “write state inspection circuit”) is integrated to the logical circuit of the VLSI unit in the conventional optically reconfigurable gate array. In general, the write state inspection circuit comprises one to three reading transistors that read the logical level of the written signal corresponding to the optically reconfigurable bit element, a wiring that externally pulls-out the logical level read by the reading transistors, and a decoder circuit that selects the optically reconfigurable bit element for executing the inspection.
Upon executing the inspection of the write state, the decoder circuit first selects the optically reconfigurable bit element as an inspection target. Further, the reading transistor reads the logical level of one-bit information on the circuit structure written by the optically reconfigurable bit element and compares the read logical level with a normal write value, thereby inspecting whether or not the logical level is normally written. This procedure is iterated for all the optically reconfigurable bit elements. If the write states of all the optically reconfigurable bit elements are normal, the inspection ends. This inspection is executed once after first setting the optical memory of the optical unit. After normally setting a physical positional relationship between the optical memory and the logical circuit chip, the write state inspection circuit is not required.
[Patent Document 1]
Japanese Unexamined Patent Application Publication No. 2002-353317
[Patent Document 2]
U.S. Pat. No. 5,959,747
[Patent Document 3]
U.S. Pat. No. 6,057,703
[Patent Document 4]
U.S. Pat. No. 6,072,608
[Non-Patent Document 1]
J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically Programmable Gate Array”, Proc. SPIE of Optics in Computing 2000, The International Society for Optical Engineering, May 2000, Vol. 4089, pp. 763-771
[Non-Patent Document 2]
J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and S. Psalt is, “Optical memory for computing and information processing”, Proc. SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, The International Society for Optical Engineering, July 1999, Vol. 3804, pp. 14-24
[Non-Patent Document 3]
J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, G. Zhou, F. Mok, “Optically Reconfigurable Gate Array”, Proceedings of the 29th Applied Imagery Pattern Recognition Workshop (AIPR '00), IEEE Computer Society, Oct. 16-18, 2000, pp. 84
[Non-Patent Document 4]
Jose Mumbru, George Panotopoulos, Arrigo Benedetti, Demetri Psaltis, Pietro Perona, “Optically Programmable FPGA Systems”, [online], on Dec. 13, 2001, California Institute of Technology Division of Engineering and Applied Science, [searched on Jul. 21, 2003,], Internet <URL: http://www.cnse.caltech.edu/Research02/reports/panotopoulos2 full.html>